ds051 (v2.0) january 25, 2001 www.xilinx.com 1 advance product specification 1-800-255-7778 ? 2001 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? 144 macrocells with 3,200 usable gates available in small footprint packages - 100-pin tqfp (81 user i/o pins) - 144-pin tqfp (117 user i/o pins) - 144-pin csp (117 user i/o pins) optimized for high-performance 2.5v systems - low power operation - multi-voltage operation advanced system features - in-system programmable - two separate output banks - superior pin-locking and routability with fastconnect ii? switch matrix - extra wide 54-input function blocks - up to 90 product-terms per macrocell with individual product-term allocation - local clock inversion with three global and one product-term clocks - individual output enable per output pin - input hysteresis on all user and boundary-scan pin inputs - bus-hold ciruitry on all user pin inputs - full ieee standard 1149.1 boundary-scan (jtag) fast concurrent programming slew rate control on individual outputs enhanced data security features excellent quality and reliability - endurance exceeding 10,000 program/erase cycles - 20 year data retention - esd protection exceeding 2,000v description the xc95144xv is a 2.5v cpld targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems. it is comprised of eight 54v18 function blocks, providing 3,200 usable gates with propagation delays of 4 ns. power estimation power dissipation in cplds can vary substantially depend- ing on the system frequency, design application and output loading. to help reduce power dissipation, each macrocell in a xc9500xv device may be configured for low-power mode (from the default high-performance mode). in addi- tion, unused product-terms and macrocells are automati- cally deactivated by the software to further conserve power. for a general estimate of i cc , the following equation may be used: i cc (ma) = mc hp (0.5) + mc lp (0.3) + mc(0.0045 ma/mhz) f where: mc hp = macrocells in high-performance (default) mode mc lp = macrocells in low-power mode mc = total number of macrocells used f = clock frequency (mhz) this calculation is based on typical operating conditions using a pattern of 16-bit up/down counters in each function block with no output loading. the actual i cc value varies with the design application and should be verified during normal system operation. figure 1 shows the above estimation in a graphical form. 0 xc95144xv high-performance cpld ds051 (v2.0) january 25, 2001 01 advance product specification r figure 1: typical i cc vs. frequency for xc95144xv 080120 200 ds051_01_012501 160 40 50 100 150 200 clock frequency (mhz) typical i cc (ma) 200 mhz 120 mhz high pe r formance lo w p ower
xc95144xv high-performance cpld 2 www.xilinx.com ds051 (v2.0) january 25, 2001 1-800-255-7778 advance product specification r figure 2: xc95144xv architecture function block outputs (indicated by the bold line) drive the i/o blocks directly. in-system programming controller jtag controller i/o blocks function block 1 macrocells 1 to 18 macrocells 1 to 18 macrocells 1 to 18 macrocells 1 to 18 jtag port 3 54 i/o/gts i/o/gsr i/o/gck i/o i/o i/o i/o 4 1 i/o i/o i/o i/o 3 ds051_02_041000 1 function block 2 54 function block 3 54 function block 4 54 macrocells 1 to 18 function block 8 54 18 18 18 18 18 fastconnect ii switch matrix
xc95144xv high-performance cpld ds051 (v2.0) january 25, 2001 www.xilinx.com 3 advance product specification 1-800-255-7778 r absolute maximum ratings recommended operation conditions quality and reliability characteristics symbol description value units v cc supply voltage relative to gnd ? 0.5 to 2.7 v v ccio supply voltage for output drivers ? 0.5 to 3.6 v v in input voltage relative to gnd (1) ? 0.5 to 3.6 v v ts voltage applied to 3-state output (1) ? 0.5 to 3.6 v t stg storage temperature (ambient) ? 65 to +150 o c t sol maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 o c t j junction temperature +150 o c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easier to achieve. during transitions, the device pins may undershoot to ? 2.0v or overshoot to +3.6v, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 ma. 2. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating condi tions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. symbol parameter min max units v ccint supply voltage for internal logic and input buffers commercial t a = 0 o c to +70 o c2.4 2.6 v industrial t a = ? 40 o c to +85 o c2.42.6 v ccio supply voltage for output drivers for 3.3v operation 3.1 3.5 v supply voltage for output drivers for 2.5v operation 2.4 2.6 v supply voltage for output drivers for 1.8v operation 1.7 1.9 v v il low-level input voltage 0 0.8 v v ih high-level input voltage 1.7 3.6 v v o output voltage 0 v ccio v symbol parameter min max units t dr data retention 20 - years n pe program/erase cycles (endurance) 10,000 - cycles v esd electrostatic discharge (esd) 2,000 - volts
xc95144xv high-performance cpld 4 www.xilinx.com ds051 (v2.0) january 25, 2001 1-800-255-7778 advance product specification r dc characteristics (over recommended operating conditions) ac characteristics symbol parameter test conditions min max units v oh output high voltage for 3.3v outputs i oh = ? 4.0 ma 2.4 - v output high voltage for 2.5v outputs i oh = ? 1.0 ma 2.0 - v output high voltage for 1.8v outputs i oh = ? 100 a 90% v ccio -v v ol output low voltage for 3.3v outputs i ol = 8.0 ma - 0.4 v output low voltage for 2.5v outputs i ol = 1.0 ma - 0.4 v output low voltage for 1.8v outputs i ol = 100 a-0.4v i il input leakage current v cc = 2.6v v ccio = 3.6v v in = gnd or 3.6v -10 a i ih i/o high-z leakage current v cc = 2.0v v ccio = 3.6v v in = gnd or 3.6v -10 a c in i/o capacitance v in = gnd f = 1.0 mhz -10pf i cc operating supply current (low power mode, active) v i = gnd, no load f = 1.0 mhz 29 ma symbol parameter xc95144xv-4 xc95144xv-5 xc95144xv-7 units min max min max min max t pd i/o to output valid - 4.0 - 5.0 - 7.5 ns t su i/o setup time before gck 3.1 - 3.7 - 4.8 - ns t h i/o hold time after gck 0 - 0 - 0 - ns t co gck to output valid - 2.0 - 2.5 - 4.5 ns f system multiple fb internal operating frequency - 250.0 - 222.2 - 125.0 mhz t psu i/o setup time before p-term clock input 0.5 - 0.7 - 1.6 - ns t ph i/o hold time after p-term clock input 1.8 - 2.0 - 3.2 - ns t pco p-term clock output valid - 4.6 - 5.5 - 7.7 ns t oe gts to output valid - 2.5 - 3.0 - 5.0 ns t od gts to output disable - 2.5 - 3.0 - 5.0 ns t poe product term oe to output enabled - 5.5 - 7.0 - 9.5 ns t pod product term oe to output disabled - 5.5 - 7.0 - 9.5 ns t ao gsr to output valid - 7.7 - 10.0 - 12.0 ns t pao p-term s/r to output valid - 8.5 - 10.5 - 12.6 ns t wlh gck pulse width (high or low) 2.0 - 2.2 - 4.0 - ns t plh p-term clock pulse width (high or low) 5.0 - 5.0 - 6.5 - ns advance information notes: 1. please contact xilinx for up-to-date information on advance specifications.
xc95144xv high-performance cpld ds051 (v2.0) january 25, 2001 www.xilinx.com 5 advance product specification 1-800-255-7778 r internal timing parameters figure 3: ac load circuit symbol parameter xc95144xv-4 xc95144xv-5 xc95144xv-7 units min max min max min max buffer delays t in input buffer delay - 1.2 - 1.5 - 2.3 ns t gck gck buffer delay - 0.2 - 0.3 - 1.5 ns t gsr gsr buffer delay - 1.2 - 2.0 - 3.1 ns t gts gts buffer delay - 2.5 - 3.0 - 5.0 ns t out output buffer delay - 1.6 - 2.0 - 2.5 ns t en output buffer enable/disable delay - 0 - 0 - 0 ns product term control delays t ptck product term clock delay - 1.6 - 1.8 - 2.4 ns t ptsr product term set/reset delay - 0.8 - 1.0 - 1.4 ns t ptts product term 3-state delay - 4.3 - 5.5 - 7.2 ns internal register and combinatorial delays t pdi combinatorial logic propagation delay - 0.4 - 0.5 - 1.3 ns t sui register setup time 1.3 - 1.5 - 2.6 - ns t hi register hold time 1.0 - 1.2 - 2.2 - ns t ecsu register clock enable setup time 1.3 - 1.5 - 2.6 - ns t echo register clock enable hold time 1.0 - 1.2 - 2.2 - ns t coi register clock to output valid time - 0.2 - 0.2 - 0.5 ns t aoi register async. s/r to output delay - 4.9 - 6.0 - 6.4 ns t rai register async. s/r recover before clock 4.0 5.0 7.5 ns t logi internal logic delay - 0.8 - 1.0 - 1.4 ns t logilp internal low power logic delay - 3.8 - 5.0 - 6.4 ns feedback delays t f fastconnect ii ? feedback delay - 1.7 - 1.8 - 3.5 ns time adders t pta incremental product term allocator delay - 0.6 - 0.7 - 0.8 ns t pta2 adjacent macrocell p-term allocator delay - 0.2 - 0.3 - 0.3 ns t slew slew-rate limited delay - 2.5 - 3.0 - 4.0 ns advance information notes: 1. please contact xilinx for up-to-date information on advance specifications. r 1 v test c l r 2 device output output type v test 3.3v 2.5v 1.8v r 1 320 ? 250 ? 10k ? r 2 360 ? 660 ? 14k ? c l 35 pf 35 pf 35 pf ds051_03_0601000 v ccio 3.3v 2.5v 1.8v
xc95144xv high-performance cpld 6 www.xilinx.com ds051 (v2.0) january 25, 2001 1-800-255-7778 advance product specification r xc95144xv i/o pins function block macro- cell tq100 tq144 cs144 bscan order bank function block macro- cell tq100 tq144 cs144 bscan order bank 1 1 - 23 h3 429 1 3 1 - 39 m3 321 1 1 2 11 16 f1 426 1 3 2 23 (1) 32 (1) l1 (1) 318 1 1 3 12 17 g2 423 1 3 3 - 41 k4 315 1 1 4 - 25 j1 420 1 3 4 - 44 n4 312 1 1 5 13 19 g3 417 1 3 5 24 33 l2 309 1 1 6 14 20 g4 414 1 3 6 25 34 l3 306 1 1 7 - --411- 3 7 - 46 l5 303 1 1 8 15 21 h1 408 1 3 8 27 (1) 38 (1) n2 (1) 300 1 1 9 16 22 h2 405 1 3 9 28 40 n3 297 1 1 10 - 31 k3 402 1 3 10 - 48 n5 294 1 1 11 17 24 h4 399 1 3 11 29 43 m4 291 1 1 12 18 26 j2 396 1 3 12 30 45 k5 288 1 1 13 -- -393- 3 13 - - - 285 - 1 14 19 27 j3 390 1 3 14 32 49 k6 282 1 1 15 20 28 j4 387 1 3 15 33 50 l6 279 1 1 16 - 35 m1 384 1 3 16 - - - 276 - 1 17 22 (1) 30 (1) k2 (1) 381 1 3 17 34 51 m6 273 1 118 -- - 378 - 3 18 - - - 270 - 2 1 - 142 c3 375 2 4 1 - 118 c9 267 2 2 2 99 (1) 143 (1) a2 (1) 372 2 4 2 87 126 a7 264 2 2 3 - --369- 4 3 - 133 a5 261 2 2 4 - 4c13662 4 4 - - - 258 - 2 5 1 (1) 2 (1) b1 (1) 363 2 4 5 89 128 d7 255 2 2 6 2 (1) 3 (1) c2 (1) 360 2 4 6 90 129 a6 252 2 2 7 - --357- 4 7 - - - 249 - 2 8 3 (1) 5 (1) d4 (1) 354 2 4 8 91 130 b6 246 2 2 9 4 (1) 6 (1) d3 (1) 351 2 4 9 92 131 c6 243 2 2 10 - 7d23482 4 10 - 135 c5 240 2 2 11 6 9e43452 4 11 93 132 d6 237 2 2 12 7 10 e3 342 2 4 12 94 134 b5 234 2 2 13 - 12 e1 339 2 4 13 - 137 a4 231 2 2 14 8 11 e2 336 2 4 14 95 136 d5 228 2 2 15 9 13 f4 333 2 4 15 96 138 b4 225 2 2 16 - 14 f3 330 2 4 16 - 139 c4 222 2 2 17 10 15 f2 327 2 4 17 97 140 a3 219 2 218- - -324- 4 18 - - - 216 - notes: 1. global control pin.
xc95144xv high-performance cpld ds051 (v2.0) january 25, 2001 www.xilinx.com 7 advance product specification 1-800-255-7778 r function block macro- cell tq100 tq144 cs144 bscan order bank function block macro- cell tq100 tq144 cs144 bscan order bank 5 1 - --213- 7 1 - --105- 5 2 35 52 n6 210 1 7 2 50 71 n12 102 1 5 3 - 59 l8 207 1 7 3 - 75 l12 99 1 5 4 - --204- 7 4 - --96- 5 5 36 53 m7 201 1 7 5 52 74 m13 93 1 5 6 37 54 n7 198 1 7 6 53 76 l13 90 1 5 7 - 66 m10 195 1 7 7 - 77 k10 87 1 5 8 39 56 k7 192 1 7 8 54 78 k11 84 1 5 9 40 57 n8 189 1 7 9 55 80 k13 81 1 5 10 - 68 n11 186 1 7 10 - 79 k12 78 1 5 11 41 58 m8 183 1 7 11 56 82 j11 75 1 5 12 42 60 k8 180 1 7 12 58 85 h10 72 1 5 13 - 70 l11 177 1 7 13 - 81 j10 69 1 5 14 43 61 n9 174 1 7 14 59 86 h11 66 1 5 15 46 64 k9 171 1 7 15 60 87 h12 63 1 5 16 - --168- 7 16 - 83 j12 60 1 5 17 49 69 m11 165 1 7 17 61 88 h13 57 1 5 18- - -162- 7 18- - -54- 6 1 - --159- 8 1 - --51- 6 2 74 106 c11 156 2 8 2 63 91 g11 48 2 6 3 - --153- 8 3 - 95 f11 45 2 6 4 - 111 b11 150 2 8 4 - 97 e13 42 2 6 5 76 110 a12 147 2 8 5 64 92 g10 39 2 6 6 77 112 a11 144 2 8 6 65 93 f13 36 2 6 7 - --141- 8 7 - --33- 6 8 78 113 d10 138 2 8 8 66 94 f12 30 2 6 9 79 116 a10 135 2 8 9 67 96 f10 27 2 6 10 - 115 b10 132 2 8 10 - 101 d13 24 2 6 11 80 119 b9 129 2 8 11 68 98 e12 21 2 6 12 81 120 a9 126 2 8 12 70 100 e10 18 2 6 13 - --123- 8 13 - 103 d11 15 2 6 14 82 121 d8 120 2 8 14 71 102 d12 12 2 6 15 85 124 a8 117 2 8 15 72 104 c13 9 2 6 16 - 117 d9 114 2 8 16 - 107 b13 6 2 6 17 86 125 b7 111 2 8 17 73 105 c12 3 2 6 18- - -108- 8 18- - - 0-
xc95144xv high-performance cpld 8 www.xilinx.com ds051 (v2.0) january 25, 2001 1-800-255-7778 advance product specification r xc95144xv global, jtag and power pins pin type tq100 tq144 cs144 i/o/gck1 22 30 k2 i/o/gck2 23 32 l1 i/o/gck3 27 38 n2 i/o/gts1 3 5 d4 i/o/gts2 4 6 d3 i/o/gts3 1 2 b1 i/o/gts4 2 3 c2 i/o/gsr 99 143 a2 tck 48 67 l10 tdi4563l9 tdo 83 122 c8 tms 47 65 n10 v ccint 2.5v 5, 57, 98 8, 42, 84, 141 b3, d1, j13, l4 v ccio 1 26, 38, 51 37, 55, 73 l7, n1, n13 v ccio 2 88 1, 109, 127 a1, a13, c7 gnd 21, 31, 44, 62, 69, 75, 84, 100 18, 29, 36, 47, 62, 72, 89, 90, 99, 108, 114, 123, 144 b2, b8, b12, c10, e11, g1, g12, g13, k1, m2, m5, m9, m12 no connects - - -
xc95144xv high-performance cpld ds051 (v2.0) january 25, 2001 www.xilinx.com 9 advance product specification 1-800-255-7778 r ordering information component availability revision history the following table shows the revision history for this document.. pins 100 144 144 type plastic tqfp plastic tqfp plastic csp code tq100 tq144 cs144 xc95144xv -7 c, i c, i c -5 (c) (c) (c) -4 (c) (c) - notes: 1. c = commercial (t a = 0 o c to +70 o c); i = industrial (t a = ? 40 o c to +85 o c). 2. ( ) parenthesis indicate future planned products. please contact xilinx for up-to-date information. date version revision 06/28/00 1.0 initial xilinx release. advance information specification. 01/25/01 2.0 added -4 performance specifications.updated i cc vs. frequency figure 1 . xc95144xv -7 tq 100 c example: temperature range number of pins package type device type speed grade device ordering options speed package temperature -7 7.5 ns pin-to-pin delay tq100 100-pin thin quad flat pack (tqfp) c = commercial t a = 0 c to +70 c -5 5 ns pin-to-pin delay tq144 144-pin thin quad flat pack (tqfp) i = industrial t a = ? 40 c to +85 c -4 4 ns pin-to-pin delay cs144 144-ball chip scale package (csp)
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